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<p>This typedef contains configuration information for the device.  
 <a href="struct_x_bram___config.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:a23d7ff9f20a32ce4fbe4eab005cfc9be"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#a23d7ff9f20a32ce4fbe4eab005cfc9be">DeviceId</a></td></tr>
<tr class="memdesc:a23d7ff9f20a32ce4fbe4eab005cfc9be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unique ID of device.  <a href="#a23d7ff9f20a32ce4fbe4eab005cfc9be">More...</a><br /></td></tr>
<tr class="separator:a23d7ff9f20a32ce4fbe4eab005cfc9be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad6d36760e863506573b858fd6cfb3382"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#ad6d36760e863506573b858fd6cfb3382">DataWidth</a></td></tr>
<tr class="memdesc:ad6d36760e863506573b858fd6cfb3382"><td class="mdescLeft">&#160;</td><td class="mdescRight">BRAM data width.  <a href="#ad6d36760e863506573b858fd6cfb3382">More...</a><br /></td></tr>
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<tr class="memitem:a75f61a0ada77e92ed76040a4556fc6d4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#a75f61a0ada77e92ed76040a4556fc6d4">EccPresent</a></td></tr>
<tr class="memdesc:a75f61a0ada77e92ed76040a4556fc6d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is ECC supported in H/W.  <a href="#a75f61a0ada77e92ed76040a4556fc6d4">More...</a><br /></td></tr>
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<tr class="memitem:a58c670c0f23257fa4521b4fc219773bc"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#a58c670c0f23257fa4521b4fc219773bc">FaultInjectionPresent</a></td></tr>
<tr class="memdesc:a58c670c0f23257fa4521b4fc219773bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is Fault Injection supported in H/W.  <a href="#a58c670c0f23257fa4521b4fc219773bc">More...</a><br /></td></tr>
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<tr class="memitem:a68ac643548b48f788d6c2f573cb5547a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#a68ac643548b48f788d6c2f573cb5547a">CorrectableFailingRegisters</a></td></tr>
<tr class="memdesc:a68ac643548b48f788d6c2f573cb5547a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is Correctable Failing Registers supported in H/W.  <a href="#a68ac643548b48f788d6c2f573cb5547a">More...</a><br /></td></tr>
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<tr class="memitem:a523f6c9b0013be3fc8cc5ab879e39035"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#a523f6c9b0013be3fc8cc5ab879e39035">CorrectableFailingDataRegs</a></td></tr>
<tr class="memdesc:a523f6c9b0013be3fc8cc5ab879e39035"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is Correctable Failing Data Registers supported in H/W.  <a href="#a523f6c9b0013be3fc8cc5ab879e39035">More...</a><br /></td></tr>
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<tr class="memitem:aaa48d2b7251ca2b7020514d29e56f97c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#aaa48d2b7251ca2b7020514d29e56f97c">UncorrectableFailingRegisters</a></td></tr>
<tr class="memdesc:aaa48d2b7251ca2b7020514d29e56f97c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is Un-correctable Failing Registers supported in H/W.  <a href="#aaa48d2b7251ca2b7020514d29e56f97c">More...</a><br /></td></tr>
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<tr class="memitem:a33d6e8224ae0b1a661e4c2dad194377c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#a33d6e8224ae0b1a661e4c2dad194377c">UncorrectableFailingDataRegs</a></td></tr>
<tr class="memdesc:a33d6e8224ae0b1a661e4c2dad194377c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is Un-correctable Failing Data Registers supported in H/W.  <a href="#a33d6e8224ae0b1a661e4c2dad194377c">More...</a><br /></td></tr>
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<tr class="memitem:ac12c18f690cc9dbc18392ee8c01c29d7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#ac12c18f690cc9dbc18392ee8c01c29d7">EccStatusInterruptPresent</a></td></tr>
<tr class="memdesc:ac12c18f690cc9dbc18392ee8c01c29d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Are ECC status and interrupts supported in H/W.  <a href="#ac12c18f690cc9dbc18392ee8c01c29d7">More...</a><br /></td></tr>
<tr class="separator:ac12c18f690cc9dbc18392ee8c01c29d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58fc68e35caa4b6e99d6203feadf3867"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#a58fc68e35caa4b6e99d6203feadf3867">CorrectableCounterBits</a></td></tr>
<tr class="memdesc:a58fc68e35caa4b6e99d6203feadf3867"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of bits in the Correctable Error Counter.  <a href="#a58fc68e35caa4b6e99d6203feadf3867">More...</a><br /></td></tr>
<tr class="separator:a58fc68e35caa4b6e99d6203feadf3867"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac31c4a853da7fc695b0a0f66e1b2b8ad"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#ac31c4a853da7fc695b0a0f66e1b2b8ad">EccOnOffRegister</a></td></tr>
<tr class="memdesc:ac31c4a853da7fc695b0a0f66e1b2b8ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is ECC on/off register supported in h/w.  <a href="#ac31c4a853da7fc695b0a0f66e1b2b8ad">More...</a><br /></td></tr>
<tr class="separator:ac31c4a853da7fc695b0a0f66e1b2b8ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4d63ef55fdf48af57677d9fd6ee8448"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#ad4d63ef55fdf48af57677d9fd6ee8448">EccOnOffResetValue</a></td></tr>
<tr class="memdesc:ad4d63ef55fdf48af57677d9fd6ee8448"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset value of the ECC on/off register in h/w.  <a href="#ad4d63ef55fdf48af57677d9fd6ee8448">More...</a><br /></td></tr>
<tr class="separator:ad4d63ef55fdf48af57677d9fd6ee8448"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae19b307a3c7a9ed5649503385272072f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#ae19b307a3c7a9ed5649503385272072f">WriteAccess</a></td></tr>
<tr class="memdesc:ae19b307a3c7a9ed5649503385272072f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is write access enabled in h/w.  <a href="#ae19b307a3c7a9ed5649503385272072f">More...</a><br /></td></tr>
<tr class="separator:ae19b307a3c7a9ed5649503385272072f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef90bb07681243210803842ba12a43da"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#aef90bb07681243210803842ba12a43da">MemBaseAddress</a></td></tr>
<tr class="memdesc:aef90bb07681243210803842ba12a43da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device memory base address.  <a href="#aef90bb07681243210803842ba12a43da">More...</a><br /></td></tr>
<tr class="separator:aef90bb07681243210803842ba12a43da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9461811eea019ba314302d12eb35c7f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#ae9461811eea019ba314302d12eb35c7f">MemHighAddress</a></td></tr>
<tr class="memdesc:ae9461811eea019ba314302d12eb35c7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device memory high address.  <a href="#ae9461811eea019ba314302d12eb35c7f">More...</a><br /></td></tr>
<tr class="separator:ae9461811eea019ba314302d12eb35c7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae96ce11672cf82713b994dc80a1a05aa"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#ae96ce11672cf82713b994dc80a1a05aa">CtrlBaseAddress</a></td></tr>
<tr class="memdesc:ae96ce11672cf82713b994dc80a1a05aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device register base address.  <a href="#ae96ce11672cf82713b994dc80a1a05aa">More...</a><br /></td></tr>
<tr class="separator:ae96ce11672cf82713b994dc80a1a05aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a390580d5224db7ed714f508b5dfdc672"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_bram___config.html#a390580d5224db7ed714f508b5dfdc672">CtrlHighAddress</a></td></tr>
<tr class="memdesc:a390580d5224db7ed714f508b5dfdc672"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device register base address.  <a href="#a390580d5224db7ed714f508b5dfdc672">More...</a><br /></td></tr>
<tr class="separator:a390580d5224db7ed714f508b5dfdc672"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>This typedef contains configuration information for the device. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="a58fc68e35caa4b6e99d6203feadf3867"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a58fc68e35caa4b6e99d6203feadf3867">&#9670;&nbsp;</a></span>CorrectableCounterBits</h2>

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          <td class="memname">int XBram_Config::CorrectableCounterBits</td>
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<p>Number of bits in the Correctable Error Counter. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>.</p>

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<a id="a523f6c9b0013be3fc8cc5ab879e39035"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a523f6c9b0013be3fc8cc5ab879e39035">&#9670;&nbsp;</a></span>CorrectableFailingDataRegs</h2>

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          <td class="memname">int XBram_Config::CorrectableFailingDataRegs</td>
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<p>Is Correctable Failing Data Registers supported in H/W. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>.</p>

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<a id="a68ac643548b48f788d6c2f573cb5547a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a68ac643548b48f788d6c2f573cb5547a">&#9670;&nbsp;</a></span>CorrectableFailingRegisters</h2>

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<p>Is Correctable Failing Registers supported in H/W. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>, and <a class="el" href="group__bram__v4__0.html#gaedbdefb6cda5c212f03271143ccf7a98">XBram_SelfTest()</a>.</p>

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<a id="ae96ce11672cf82713b994dc80a1a05aa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae96ce11672cf82713b994dc80a1a05aa">&#9670;&nbsp;</a></span>CtrlBaseAddress</h2>

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<p>Device register base address. </p>

<p class="reference">Referenced by <a class="el" href="xbram__example_8c.html#a324ee6c433c84befd0c6b7b6f5483246">BramExample()</a>, <a class="el" href="xbram__intr__example_8c.html#a02808f594e2c936129bed18559bc0e97">BramIntrExample()</a>, <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>, <a class="el" href="group__bram__v4__0.html#gaa4ac1ca5c9c05eabbdea77f35ba9ac5a">XBram_InterruptClear()</a>, <a class="el" href="group__bram__v4__0.html#ga9ce680e885511fdd26b6818b71b145c4">XBram_InterruptDisable()</a>, <a class="el" href="group__bram__v4__0.html#ga4210a263bd85db259a74c20cd0b0176c">XBram_InterruptEnable()</a>, <a class="el" href="group__bram__v4__0.html#gafec7418ceae662672c03a938290da9dd">XBram_InterruptGetEnabled()</a>, <a class="el" href="group__bram__v4__0.html#ga3880bb684ad362c6bd289f3e76a98b59">XBram_InterruptGetStatus()</a>, and <a class="el" href="group__bram__v4__0.html#gaedbdefb6cda5c212f03271143ccf7a98">XBram_SelfTest()</a>.</p>

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<a id="a390580d5224db7ed714f508b5dfdc672"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a390580d5224db7ed714f508b5dfdc672">&#9670;&nbsp;</a></span>CtrlHighAddress</h2>

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<p>Device register base address. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad6d36760e863506573b858fd6cfb3382">&#9670;&nbsp;</a></span>DataWidth</h2>

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<p>BRAM data width. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>, and <a class="el" href="group__bram__v4__0.html#gaedbdefb6cda5c212f03271143ccf7a98">XBram_SelfTest()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#a23d7ff9f20a32ce4fbe4eab005cfc9be">&#9670;&nbsp;</a></span>DeviceId</h2>

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<p>Unique ID of device. </p>

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<a id="ac31c4a853da7fc695b0a0f66e1b2b8ad"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac31c4a853da7fc695b0a0f66e1b2b8ad">&#9670;&nbsp;</a></span>EccOnOffRegister</h2>

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<p>Is ECC on/off register supported in h/w. </p>

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<a id="ad4d63ef55fdf48af57677d9fd6ee8448"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad4d63ef55fdf48af57677d9fd6ee8448">&#9670;&nbsp;</a></span>EccOnOffResetValue</h2>

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<p>Reset value of the ECC on/off register in h/w. </p>

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<a id="a75f61a0ada77e92ed76040a4556fc6d4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a75f61a0ada77e92ed76040a4556fc6d4">&#9670;&nbsp;</a></span>EccPresent</h2>

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<p>Is ECC supported in H/W. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>, and <a class="el" href="group__bram__v4__0.html#gaedbdefb6cda5c212f03271143ccf7a98">XBram_SelfTest()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac12c18f690cc9dbc18392ee8c01c29d7">&#9670;&nbsp;</a></span>EccStatusInterruptPresent</h2>

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          <td class="memname">int XBram_Config::EccStatusInterruptPresent</td>
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<p>Are ECC status and interrupts supported in H/W. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#a58c670c0f23257fa4521b4fc219773bc">&#9670;&nbsp;</a></span>FaultInjectionPresent</h2>

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          <td class="memname">int XBram_Config::FaultInjectionPresent</td>
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<p>Is Fault Injection supported in H/W. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#aef90bb07681243210803842ba12a43da">&#9670;&nbsp;</a></span>MemBaseAddress</h2>

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          <td class="memname">u32 XBram_Config::MemBaseAddress</td>
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<p>Device memory base address. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae9461811eea019ba314302d12eb35c7f">&#9670;&nbsp;</a></span>MemHighAddress</h2>

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          <td class="memname">u32 XBram_Config::MemHighAddress</td>
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<p>Device memory high address. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>.</p>

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<a id="a33d6e8224ae0b1a661e4c2dad194377c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a33d6e8224ae0b1a661e4c2dad194377c">&#9670;&nbsp;</a></span>UncorrectableFailingDataRegs</h2>

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          <td class="memname">int XBram_Config::UncorrectableFailingDataRegs</td>
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<p>Is Un-correctable Failing Data Registers supported in H/W. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>.</p>

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<a id="aaa48d2b7251ca2b7020514d29e56f97c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aaa48d2b7251ca2b7020514d29e56f97c">&#9670;&nbsp;</a></span>UncorrectableFailingRegisters</h2>

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          <td class="memname">int XBram_Config::UncorrectableFailingRegisters</td>
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<p>Is Un-correctable Failing Registers supported in H/W. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>.</p>

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<a id="ae19b307a3c7a9ed5649503385272072f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae19b307a3c7a9ed5649503385272072f">&#9670;&nbsp;</a></span>WriteAccess</h2>

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          <td class="memname">int XBram_Config::WriteAccess</td>
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<p>Is write access enabled in h/w. </p>

<p class="reference">Referenced by <a class="el" href="group__bram__v4__0.html#gab305438b0844ddb20139878c21ef0e6b">XBram_CfgInitialize()</a>.</p>

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